IP CATALOG
High-Performance Interface & Subsystem IP for Real-World Systems
A comprehensive family of digital interfaces, protocol controllers, and subsystem building blocks engineered for FPGA and ASIC integration.
Unmatched throughput with 64 GT/s scalable lane architectures
Standards-compliant PHY + Controller + CXL 3.0 support
Portable, modular IP optimized for FPGA prototyping and ASIC transition
Designed to complement our PCIe/CXL flagship platform, our interface and subsystem IPs provide the connectivity, streaming, and control infrastructure required in high-speed compute, networking, storage, and mission-critical systems.
ARCHITECTURE OVERVIEW
A Complete, Modular Interconnect Architecture
Our PCIe & CXL IP suite is engineered as a modular, standards-aligned architecture that supports fast integration, portable scaling,
and deterministic verification across FPGA and ASIC platforms.
Building Blocks
- PCIe 6/7 Controller IP — Transaction, Data Link, Physical coding layers
- PCIe 6/7 PHY IP — PAM4 encoding, equalization, link training, LTSSM
- CXL 3.0 Controller IP — CXL.io, CXL.cache, CXL.mem protocols
- Subsystem Utilities — DMA engines, BAR management, lane aggregation, error handling
- Verification Environment — Compliance testbench, coverage agents, protocol monitors
- Reference Platforms — FPGA test designs for AMD, Intel, Lattice
ARCHITECTURE OVERVIEW
Verified for Standards Compliance & Interoperability
Our verification methodology integrates constrained-random testing, coverage-driven validation, and automated YAML-based
test flows to ensure protocol correctness and interoperability across diverse platforms.
Full PCI-SIG Compliance
Validated for LTSSM transitions, link training, equalization, encoding, and error recovery.
CXL 3.0 Protocol Coverage
Verified for CXL.io, cache/mem flows, coherency, ordering, and transaction-level correctness.
FPGA-Proven Across Vendors
Tested on multiple FPGA families for portability and predictable ASIC migration.
Designed for Fast Integration, Reliable Performance, and Reuse
Modular Architecture
All IPs follow a consistent architecture, register interface pattern, and documentation style enabling rapid adoption and predictable integration.
FPGA-Proven, ASIC-Ready
Each IP has been validated in real customer deployments, supporting predictable timing closure and efficient ASIC handoff.
Seamless Co-Design Compatibility
Subsystem IPs integrate cleanly with PCIe/ CXL blocks, DMA engines, memory subsystems, and embedded firmware flows.
Modular Architecture
All IPs follow a consistent architecture, register interface pattern, and documentation style enabling rapid adoption and predictable integration.
FPGA-Proven, ASIC-Ready
Each IP has been validated in real customer deployments, supporting predictable timing closure and efficient ASIC handoff.
Seamless Co-Design Compatibility
Subsystem IPs integrate cleanly with PCIe/ CXL blocks, DMA engines, memory subsystems, and embedded firmware flows.
PACKAGING & DELIVERABLES
Complete IP Delivery Packages for Fast Engineering Adoption
Deliverables include:
- Synthesizable RTL (Verilog/VHDL)
- Configurable parameters + documentation
- Timing constraints (SDC/XDC)
- Simulation models + testbenches
- Integration wrappers for common platforms
- Driver APIs (where applicable)
- Compliance and protocol checklists
- Bring-up guides for AMD/Intel/Lattice FPGAs
Licensing:
- Perpetual project licenses
- Multi-project corporate licensing
- Optional maintenance + update cycles
Our FPGA/SoC Design Approach
JESD204C @ 32 Gbps per lane
Deterministic latency and deterministic subclass support.
100G UDP Stack
Line-rate packet processing with FPGA-optimized microarchitectures.
ARINC 818-2 / 818-3
Verified video transport up to 12 Gbps with programmable VCID mapping.
USE CASES
Built for High-Performance Systems
Data Center & HPC
Ultra-low-latency interconnects for high-performance compute clusters.
AI Accelerators & ML Engines
High-bandwidth link interfaces for GPU/TPU-class architectures.
SmartNICs & DPUs
Offload engines for programmable networking devices using PCIe/CXL links.
Storage & Memory Expansion
CXL-based pooling, tiered memory, and composable disaggregated architectures.
Interface & Subsystem IP
We help Interface & Subsystem IP companies accelerate PCIe/CXL adoption with reusable, scalable, ASIC-ready architectures.